The way its programmed consumes lower level of power consumption in the range of 50.4 nw and delay of 25.2 ns and also modern adder structure with 6T type was used to implement the intermediate blocks of multiplier in FPU block as part of computing partial products. A 32 bit representation of IEEE 754 results of FPU is stored in the data storage and this process optimize the critical path between blocks. The floating point unit defined with modern FPGAR (Reconfigurable FPGA) increase the speed of computation and enables the flexibility and adopted to the hardware reconfigurable models. The main architecture is constructed using top level design with individual blocks defined as a part of it. The FPU arithmetic unit has the blocks to perform the computations like addition, Multiplication and division operation. Hence it is easily analyzed in FPGAR devices and also this work insists the importance of redefining the architecture with reduction of critical path delay. The bio medical signals are converted into IEEE 754 format as BIF. The present trends of portable devices for medical applications need occupancy of smaller area with long span time life of battery. This paper describes the floating point arithmetic unit and insists the importance of it, in real time signal processing. “The technology defined today might be redefined tomorrow”- from the quotes, in the modern era redefining the architecture with the optimization of area, delay and reduction of power is focused more than fixed models.
All the results are calculated in Xilinx ISE 12.4 design suite. Various floating point multiplier architectures used in MAC unit are pipelined floating point multiplier carry save, carry look ahead and ripple carry multipliers. Finally MAC unit is made with the help of different floating point multiplier architectures to obtain the best results in terms of area, speed and power. Various floating point multipliers are designed with the help of adders such as Carry look ahead, Carry save, Carry skip and then their individual performance analysis is done on the basis of power, speed, and area. In this research work MAC unit is proposed. In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format. MAC unit basically consists of Multiplier, adder and an accumulator unit.
The speed of the MAC unit determines the overall performance of the system. In order to meet the requirements in real time DSP applications MAC unit is required.
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